the gm71v(s)17800c/cl is the new generation dynamic ram organized 2,097,152 x 8 bit. gm71v(s)17800c/cl has realized higher density, higher performance and various functions by utilizing advanced cmos process technology. the gm71v(s)17800c/cl offers fast page mode as a high speed access mode. multiplexed address inputs permit the gm71v(s)17800c/cl to be packaged in standard 400 mil 28pin plastic soj, and standard 400mil 28pin plastic tsop ii. the package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. description features * 2,097,152 words x 8 bit organization * fast page mode capability * single power supply (3.3v+/-0.3v) * fast access time & cycle time * low power active : 468/432/396mw (max) standby : 7.2mw (cmos level : max) 0.54 mw (l- version : max) * ras only refresh, cas before ras refresh, hidden refresh capability * all inputs and outputs ttl compatible * 2048 refresh cycles/32ms * 2048 refresh cycles/128ms (l-version) * self refresh operation (l-version) * battery back up operation (l- version) pin configuration 2,097,152 words x 8 bit cmos dynamic ram 28 soj v cc i/o0 i/o1 i/o2 i/o3 1 2 3 4 5 we ras a10 a0 a1 7 8 9 10 11 6 a2 a3 v cc 12 13 14 v ss i/o7 i/o6 i/o5 i/o4 24 25 26 27 28 oe a8 a7 a6 18 19 20 21 22 cas 23 a5 a4 v ss 15 16 17 nc a9 ( top view) v cc i/o0 i/o1 i/o2 i/o3 1 2 3 4 5 we ras a10 a0 a1 7 8 9 10 11 6 a2 a3 v cc 12 13 14 v ss i/o7 i/o6 i/o5 i/o4 24 25 26 27 28 oe nc a8 a7 a6 18 19 20 21 22 cas 23 a5 a4 v ss 15 16 17 a9 28 tsop ii ( unit: ns) gm71v(s)17800c/cl-5 gm71v(s)17800c/cl-6 gm71v(s)17800c/cl-7 t rac t cac t rc t pc 50 60 13 15 90 110 35 40 70 18 130 45 GM71V17800C gm71vs17800cl rev 0.1 / apr ? 01
GM71V17800C gm71vs17800cl rev 0.1 / apr ? 01 pin description pin function pin function a0-a10 a0-a10 i/o0-i/o7 ras we v cc v ss nc address inputs refresh address inputs data input / data output row address strobe read/write enable power (+3.3v) ground no connection ordering information type no. access time package gm71v(s)17800cj/clj-5 gm71v(s)17800cj/clj-6 gm71v(s)17800cj/clj-7 50 ns 60ns 70ns 400 mil 28 pin plastic soj cas column address strobe oe output enable 50 ns 60ns 70ns 400 mil 28 pin plastic tsop ii absolute maximum ratings p d 1.0 power dissipation w symbol parameter rating unit t a t stg v in/out v cc i out 0 ~ + 70 -55 ~ + 125 50 ambient temperature under bias storage temperature (plastic) voltage on any pin relative to v ss supply voltage relative to v ss short circuit output current c c v v ma -0.5 ~ + 4.6 gm71v(s)17800ct/clt-5 gm71v(s)17800ct/clt-6 gm71v(s)17800ct/clt-7 -0.5 ~ +4.6 recommended dc operating conditions (t a = 0 ~ + 70c) symbol parameter unit v cc v ih v il supply voltage input high voltage input low voltage v v v max 3.6 vcc +0.3 0.8 typ 3.3 - - min 3.0 2.0 -0.3 note: all voltage referred to vss .
GM71V17800C gm71vs17800cl rev 0.1 / apr ? 01 dc electrical characteristics (v cc = 3.3v+/-0.3, vss = 0v, t a = 0 ~ 70c) note: 1. i cc depends on output load condition when the device is selected. i cc (max) is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. address can be changed once or less while cas = v ih . 4. cas = l (<=0.2v) while ras = l (<=0.2v). 5. l-version. symbol parameter note v oh v ol output level output "h" level voltage (i out = -2 ma ) unit max v cc 0.4 min 2.4 0 output level output "l" level voltage (i out = 2 ma ) i cc1 operating current average power supply operating current (ras, cas cycling : t rc = t rc min) i cc2 standby current (ttl) power supply standby current (ras, cas = v ih , d out = high-z) 2 - i cc3 ras only refresh current average power supply current ras only refresh mode ( t rc = t rc min) i cc4 i cc5 standby current (cmos) power supply standby current (ras, cas >= v cc - 0.2v, d out = high-z) 1 - i cc6 cas-before-ras refresh current ( t rc = t rc min) 150 - i cc7 i l(i) 10 -10 i l(o) 10 -10 input leakage current any input (0v <= v in <= 4.6v) output leakage current (d out is disabled, 0v <= v out <= 4. 6v) i cc9 self-refresh mode current (ras, cas<=0.2v , d out = high-z) 250 - fast page mode current average power supply current fast page mode ( t pc = t pc min) i cc8 110 - 50 ns 60 ns 70 ns 100 90 - - - 110 - 50 ns 60 ns 70 ns 100 90 - - 100 - 50 ns 60 ns 70 ns 90 85 - 110 - 50 ns 60 ns 70 ns - - 100 90 v v ma ma 5 - standby current ras = v ih cas = v il d out = enable ma 1 ua ua ua ua battery back up operating current (standby with cbr refresh) ( t rc =62.5us , t ras <= 0.3 us, d out = high-z) 400 - 4,5 ua ma 1, 2 ma 2 ma 1, 3 ma 5 5
GM71V17800C gm71vs17800cl rev 0.1 / apr ? 01 read, write, read-modify-write and refresh cycles (common parameters) capacitance (v cc = 3.3v+/-0.3v, t a = 25c) symbol parameter note c i1 c i2 c i/o input capacitance (address) input capacitance (clocks) output capacitance (data-in/out) 1 1 1, 2 unit pf pf pf max 5 7 7 min - - - note: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. cas = v ih to disable d out . ac characteristics (v cc = 3.3v+/-0.3v, t a = 0 ~ + 70c, vss = 0v, note 1, 2,18) test conditions input rise and fall times : 5 ns output timing reference levels : 0.8v, 2.0v input timing reference levels : 0.8v, 2.0v output load : 1ttl gate + c l (100 pf ) (including scope and jig) symbol parameter note max unit min max min max min t rc random read or write cycle time 90 - 110 - 130 - t rp ras precharge time 30 - 40 - 50 - t ras ras pulse width 50 10,000 60 10,000 70 10,000 t cas cas pulse width 10,000 10,000 10,000 15 18 t asr row address set up time 0 - - - 0 0 t rah row address hold time 8 - - - 10 10 t asc column address set-up time 0 - - - 0 0 t cah column address hold time - - - 10 15 t rcd ras to cas delay time 18 45 45 52 20 20 3 t rad ras to column address delay time 13 30 30 35 15 15 4 t rsh ras hold time 13 - - - 15 18 t csh cas hold time 50 - - - 60 70 t crp cas to ras precharge time 5 - - - 5 5 t t transition time (rise and fall) 3 50 50 50 3 3 7 t dzo oe delay time from d in 0 - - - 0 0 t dzc cas delay time from d in 0 - - - 0 0 gm71v(s)17800 c/cl-5 oe to d in delay time 13 - - - 15 18 5 6 6 t cp cas precharge time 8 - 10 - 13 - t odd gm71v(s)17800 c/cl-6 gm71v(s)17800 c/cl-7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13 8
GM71V17800C gm71vs17800cl rev 0.1 / apr ? 01 read cycle write cycle symbol parameter note max unit min max min - 60 - 70 - 15 - 18 - 30 - 35 0 - 0 - 0 - - 0 8,9 9,10,17 9,11,17 - 15 - 18 9 12 gm71v(s)17800 c/cl-6 gm71v(s)17800 c/cl-7 5 - - 5 12 30 - - 35 15 15 13 - - 30 - - 35 0 - - 0 15 15 13 - - 3 - - 3 3 - - 3 15 - - 18 access time from ras access time from cas access time from address read command setup time read command hold time to cas access time from oe read command hold time to ras column address to ras lead time output buffer turn-off time column address to cas lead time cas to output in low-z output buffer turn-off time to oe output data hold time output data hold time from oe cas to d in delay time 5 max min - 50 - 13 - 25 0 - 0 - - 13 gm71v(s)17800 c/cl-5 5 - 25 - 13 - 25 - 0 - 13 - 3 - 3 - 13 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns symbol parameter note max unit min max min 0 - 0 - 10 - 15 - 10 - 10 - 15 - 18 - 15 - - 18 0 - - 0 t rac t cac t aa t rcs t rch t oac t rrh t ral t off t cal t clz t oez t oh t oho t cdd t wcs t wch t wp t rwl t cwl t ds t d h 10 - - 15 15 15 write command setup time write command hold time write command pulse width write command to ras lead time write command to cas lead time data-in setup time data-in hold time 14 gm71v(s)17800 c/cl-6 gm71v(s)17800 c/cl-7 ns min 0 - - 8 - - - 0 - - max gm71v(s)17800 c/cl-5 ns ns ns ns ns ns 8 13 13 8
GM71V17800C gm71vs17800cl rev 0.1 / apr ? 01 read- modify-write cycle refresh cycle fast page mode cycle symbol parameter note max unit min max min t rwc 155 - 181 - t rwd 85 - 98 - t cwd 40 - 46 - t awd 55 - 63 - 14 14 14 t oeh 15 - 18 - read-modify-write cycle time ras to we delay time cas to we delay time column address to we delay time oe hold time from we gm71v(s)17800 c/cl-6 gm71v(s)17800 c/cl-7 ns ns ns ns ns min 131 - 73 - 36 - 48 - 13 - max gm71v(s)17800 c/cl-5 symbol parameter note max unit min max min t csr 5 - 5 - ns t chr 10 - 10 - ns t rpc 5 - 5 - ns gm71v(s)17800 c/cl-6 gm71v(s)17800 c/cl-7 t wrp 0 - 0 - ns t wrh 10 - 10 - ns cas setup time (cas-before-ras refresh cycle) cas hold time (cas-before-ras refresh cycle) ras precharge to cas hold time we setup time (cas-before-ras refresh cycle) we hold time (cas-before-ras refresh cycle) min 5 - 8 - 5 - gm71v(s)17800 c/cl-5 0 - 10 - max symbol parameter note max unit min max min t pc 40 - 45 - ns t rasp ns t acp 35 - 40 - ns t rhcp ns 9,17 - - 16 100,000 100,000 - - 35 40 gm71v(s)17800 c/cl-6 gm71v(s)17800 c/cl-7 access time from cas precharge ras hold time from cas precharge fast page mode ras pulse width fast page mode cycle time min 35 - 30 - - - 30 gm71v(s)17800 c/cl-5 max 100,000
GM71V17800C gm71vs17800cl rev 0.1 / apr ? 01 self refresh mode(l-version) fast page mode read-modify-write cycle refresh symbol parameter note max unit min max min t prwc 85 - 96 - ns t cpw 60 - 68 - ns 14 fast page mode read-modify-write cycle time we delay time from cas precharge gm71v(s)17800 c/cl-6 gm71v(s)17800 c/cl-7 gm71v(s)17800 c/cl-5 max min 76 - 53 - symbol parameter note t ref t ref 2048 cycles 2048 cycles refresh period refresh period(l-series) symbol parameter note max unit min max min t rass 100 - 100 - t rps ras precharge time(self-refresh) 110 - 130 - ns t chs -50 - -50 - ns ras pulse width(self-refresh) cas hold time(self-refresh) gm71vs17800 cl-6 gm71vs17800 cl-7 us max min 100 - 90 - -50 - gm71vs17800 cl-5 32 32 - - 128 128 - - 32 - 128 - max min max min gm71v(s)17800 c/cl-6 gm71v(s)17800 c/cl-7 gm71v(s)17800 c/cl-5 max min ms ms unit
GM71V17800C gm71vs17800cl rev 0.1 / apr ? 01 ac measurements assume t t = 5 ns an initial pause of 200ua is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing ras-only refresh or cas-before- ras refresh). if the internal refresh counter is used, a minimum of eight cas-before-ras refresh cycles are required. operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only; if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . either t odd or t cdd must be satisfied. either t dzo or t dzc must be satisfied. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih (min) and v il (max). assumes that t rcd <= t rcd (max) and t rad <= t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. measured with a load circuit equivalent to 1ttl loads and 100pf.(v oh = 2.0v , v= 0.8v) assumes that t rcd >= t rcd (max) and t rad <= t rad (max). assumes that t rcd <= t rcd (max) and t rad >= t rad (max). either t rch or t rrh must be satisfied for a read cycles. t off (max) and t oez (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. t wcs , t rwd , t cwd and t awd and t cpw are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only; if t wcs >= t wcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t rwd >= t rwd (min), t cwd >= t cwd (min), and t awd >= t awd (min) or t cwd >= t cwd (min), t awd >= t awd (min), and t cpw >= t cpw (min), the cycle is a read -modify- write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. these parameters are referred to cas leading edge in early write cycle and to we leading edge in a delayed write or a read modify write cycle. t rasp defines ras pulse width in fast page mode cycles. access time is determined by the longer of t aa or t cac or t acp . in delayed write or read-modify-write cycles, oe must disable output buffer prior to applying data to the device. after ras is reset, if t oeh >= t cwl , the i/o pin will remain open circuit (high impedance): if t oeh <= t cwl , invalid data will be out at each i/o. notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18.
GM71V17800C gm71vs17800cl rev 0.1 / apr ? 01 package dimensions unit: inches (mm) 28 soj 28 tsop (type ii) 0.405(10.29) max 0.394(10.03) min 0.455(11.56) min 0.471(11.96) max 0.730(18.54) max 0.720(18.28) min 0.020(0.50) max 0.012(0.30) min typ 0.050(1.27) 0.007(0.18) max 0.003(0.08) min 0.047(1.20) max 0.041(1.05) max 0.037(0.95) min 0.024(0.60) max 0.016(0.40) min 0.008(0.21) max 0.004(0.12) min 0 ~ 5 ? 0.395(10.03) min 0.435(11.06) min 0.445(11.30) max 0.366(9.30) min 0.375(9.55) max 0.025(0.64) min 0.405(10.29) max 0.032(0.81) max 0.026(0.66) min typ 0.050(1.27) 0.020(0.50) max 0.015(0.38) min 0.148(3.75) max 0.128(3.25) min 0.710(18.04) min 0.720(18.30) max 0.083(2.10) min
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